1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an AC parameter control technology of a semiconductor device.
2. Description of the Related Art
In the present specification, a semiconductor memory device will be explained for example.
In general, a semiconductor memory device such as a DRAM is packaged by stacking a plurality of semiconductor chips (or dies) to achieve a large capacity of data storage in a limited area. When compared to a semiconductor memory device having a single semiconductor chip packaged (a single die package: SDP), in a semiconductor memory device having plural semiconductor chips stack-packaged, e.g. a dual die package (DDP) having two chips or a quad die package (QDP) having four chips, bonding wires may differ in length for respective stacked semiconductor chips.
FIG. 1 is a side view schematically illustrating a semiconductor memory device (DDP) in which two semiconductor chips are stack-packaged.
Referring to FIG. 1, a bonding wire W1 for connecting a package substrate with the semiconductor chip stacked first on the package substrate may be shorter than a bonding wire W2 for connecting the package substrate with the semiconductor chip stacked second over the package substrate. Therefore, when signals are outputted from the respective semiconductor chips for the same use, timing differences are caused in the signals due to differences in the lengths of the bonding wires W1 and W2. That is to say, the signal outputted from the first stacked semiconductor chip and the signal outputted from the second stacked semiconductor chip are finally transmitted to an external controller at different times due to different positional conditions.
For example, in a semiconductor memory device using a delay locked loop (DLL), data strobe signals are transferred from a plurality of stacked semiconductor chips through bonding wires and are finally provided to an external controller through a package substrate. At this time, the data strobe signal outputted from a semiconductor chip stacked at the bottom is provided to the external controller through a relatively short bonding wire, and the data strobe signal outputted from a semiconductor chip stacked at the top is provided to the external controller through a relatively long bonding wire. Since different delay values are applied to the respective data strobe signals outputted from the plurality of stacked semiconductor chips due to differences in the lengths of the bonding wires, the respective data strobe signals reach the external controller at different times. A parameter tDQSCK that represents a skew between an external clock signal and a data strobe signal is prescribed in a specification for a proper operation of a semiconductor memory device. In this regard, if the parameter tDQSCK goes beyond a defined range due to different delay values as described above, the semiconductor memory device may malfunction in a read operation.
In order to prevent the above malfunction, the delay amounts of DLLs included in respective semiconductor chips may be corrected in correspondence to positional conditions. That is to say, in the conventional art, the delay amounts of the DLLs included in the remaining stacked semiconductor chips are corrected based on the delay amount of the DLL included in a lowermost semiconductor chip. To this end, correction circuits are provided in the remaining semiconductor chips excluding the lowermost semiconductor chip. Fuse circuits may be used as the correction circuits, and the delay amounts of the DLLs are corrected using the output signals of the fuse circuits through a fuse cutting process. However, in the case where the correction circuits are provided as described above, since an additional process such as the fuse cutting process is to be performed, the manufacturing costs increase and the manufacturing period is lengthened. Moreover, since the semiconductor chips (the upper stacked semiconductor chips) with the correction circuits and the semiconductor chip (the lowermost semiconductor chip) without a correction circuit are stack-packaged, the respective chips are to be manufactured through different mask patterning processes. Hence, the manufacturing costs and the manufacturing time may further increase.